The Multiple Roles of Bypass Capacitors
Charles Eidsness
Device manufacturers generally provide a DC specification for the minimum and maximum operating voltages for a specific device (unfortunately they don't usually provide and AC spec, but that's a topic for another future article). This article explores what could potentially go wrong when these operating limits are not met.
Nanju Na examines some of the effects of power-supply noise on an IC in her Ph.D. Thesis "Modeling and Simulation of Planes in Electronic Packages". This first few items in the list below borrow liberally from Nanju's Thesis.
Of particular interest is that all of the potential issues listed below fall into the "Super-Scary" category, they are all very hard to detect and debug. It's much easier to trouble-shoot a problem that fails spectacularly than one that will only fails under very specific conditions dependent on a large set of variables.
1. Data Bit-Error (or Clock / Control Signal Error) Due to Power Supply Noise on Signals
This is probably the most straight forward reason for designing a low noise Power-Distribution-System (PDS). When a CMOS driver is driving high there is a low-impedance connection between the power rails and the driven signal (or when driving low there is a low impedance connection between ground and the signal). Any power/ground noise will be directly coupled onto a driven signal (minus any device specific attenuation), reducing the signal's noise margin. If this noise on its own, or added to other noise sources exceeds the receiver's threshold voltage an erroneous logic level may result. Clock signals are particularly sensitive, with any added noise during a transition potentially resulting in a non-monotonic edge and a "double clock".
2. Variation in Propagation Delay
The propagation delay through a CMOS gate will vary with the gate's power supply voltage level. This variation can be described by the formula below (from Nanju Na's thesis linked to above). This is why the min and max timing requirements of a device are defined at specific power-supply voltages. In a system with tight timing restrictions this could have a detrimental result (like a DDR interface for example). Note that as the voltage is lowered the propagation delay variance increases, lower core voltage rails 90nm (and 65nm) devices are more susceptible to variances than higher voltage technologies.
3. Variation in Clock Skew and Addition of Jitter
In most CMOS receivers the main power supply voltage is used to derive the reference (switching) voltage. If the voltage rail powering a clock receiver varies over time it will alter the reference voltage and relative clock skew. This will also increase the jitter as seen by the receiver. The following equations demonstrate how a varying Vdd supply can affect clock skew and jitter, ignoring most device parasitics. (Also from Nanju Na's Thesis)
4. ESD Protection Diode Conduction
If the voltage difference between a signal driving a receiver and the receiver's power supply is greater than the threshold voltage of the device's ESD diode's the diodes will turn on. This is usually caused by excessive overshoot or undershoot on a signal but can also be caused by power supply noise, i.e. if the voltage rail on the driver is varying to a different degree than the voltage supply of the receiver there can be a voltage difference between the driver's and receiver's power pins. If ESD Protection diodes conduct they can limit the life of a device. Howard Johnson has written a short article on this phenomenon; (For Your) Protection. When conducting ESD protection diodes can draw a lot of current which will further exasperate the problem.
5. Low Impedance Signal Return Current Path
Signal return currents can be conducted through decoupling capacitors. For instance, when a voltage plane is used as a signal reference with no decoupling capacitors these return currents would flow through the IC's parasitic capacitance (and internal decoupling) which will result in even more noise on the PDS within the IC. This return path also has a larger impedance than a PCB mounted decoupling capacitor which will result in degraded Signal Integrity.