eispice is a clone of the Berkley SPICE 3 Simulation Engine. It was originally targeted toward PCB level Signal Integrity Simulation; simulating IBIS model defined devices, transmission lines, and passive termination but the scope of the tool has been slowly expanding to include more general purpose circuit simulation features.

The Simulator

The simulation engine is written in C and utilizes the SuperLU matrix library for solving the MNA Matrices. It should run faster than Berkley Spice for most IBIS based SI simulations (it's difficult to directly compare them because spice doesn't directly support IBIS models).


eispice contains a subset of standard spice3 device models. The intent is to one day be completely compliant with models available in the basic spice3f5 release. eispice also includes a set of unique models like direct IBIS model support, Python based Behavioral models, non-linear capacitors, etc. Refer to the User's Manual for more details about what's available in the current release.


Other than being the only Open Source simulator that provides native IBIS model support, the most unique feature of eispice is its Python based front-end. The eispice simulator is wrapped into a Python Module (the simulator itself is written in C) which makes it possible to use the Python language to control simulations and process results. For those familiar with Berkley Spice and not Python; a Python shell can be used in place of the nutmeg and Python scripts can be run like batch-mode SPICE.

One of the powers of Python is the ability to integrate different Python Modules. A great example of this is Thomas' MyHDL/eispice Mixed-Mode Example.

The Plotter

eispice includes a very simple plot utility or you can use the Python Plotting tool of your choice, e.g. matplotlib.


If you have any suggestions on how to improve this tool or questions about how to use it please send me an email. You can reach me at or better yet, join the Mailing List and post any comments, questions, or suggestions there.

Recent Mailing List Activity

New in the Latest Development Release

  • Migrated to Fortran 95 from Fortran 77 as the default compiler (will still build with Fortran 77).

New in the Latest Release

  • Lots of bug-fixes and performance improvements.
  • Added a non-linear capacitor model.
  • Added a Gaussian Pulse waveform which better represents a real digital signal (compared to a PWL).
  • Added a simple diode model.
  • Added Python doc-strings (built in help) to most classes, functions, and modules.
  • Changed the module naming scheme to be more descriptive and not make a big mess out of the namespace.
  • Improved IBIS model support and performance.
  • Added device library database tools.
  • Migrated to FORTRAN77 based BLAS and LAPACK libraries.

Planned for the Next Release

  • Add the remaining semi-conductor devices included in the base spice3f5 release.
  • Add a 2D BEM simulator for the W-Element creation.
  • Finish the W-Element Multi-Conductor, Frequency Dependent Transmission Line Model.